A ferroelectric thin film storage transistor is a non-volatile memory under development. A schematic diagram illustrating a structure of a conventional ferroelectric thin film storage transistor is shown in FIG. 1. The ferroelectric thin film storage transistor includes a gate 12, a ferroelectric layer 14, a source 16 and a drain 18. Under certain voltage conditions, a semiconductor channel 19 is formed between the source 16 and the drain 18. In addition, in order to prevent electric charges in the semiconductor channel 19 from diffusing into the ferroelectric layer 14, it is also generally possible to dispose a dielectric layer 15 between the ferroelectric layer 14 and the semiconductor channel 19.
By controlling the voltages applied to the gate 12, the source 16, and the drain 18, a predetermined direction of polarization can be rendered on the ferroelectric layer 14, thereby writing data “1” or “0”. As can be clearly seen from FIG. 1, since the channel through which an electric current flows is parallel to the surface of the substrate, the contact surface between the source 16 and the first conductive structure 111 as well as the contact surface between the drain 18 and the second conductive structure 112 are also parallel to the surface of the substrate 10. In order to lower circuit resistance, usually the contact surfaces, the gate 12 and the ferroelectric layer 14 must maintain a sufficient area, thus occupying a lot of chip area. As a result, the use of such horizontal ferroelectric thin film storage transistors makes it difficult to form sufficient memory cells in a limited area of the chip. Therefore, it is one of the objectives in this disclosure to improve drawbacks of conventional techniques.